ESD Design Engineer

Apple   •  

Santa Clara, CA

Industry: Business Services


8 - 10 years

Posted 393 days ago

ESD Design Engineer

  • Job Number: 55488711
  • Santa Clara Valley, California, United States
  • Posted: 25-Aug-2017
  • Weekly Hours: 40.00

Job Summary

In this highly visible role, you will take ownership of the ESD and Latch-Up requirements of all ICs developed by and for Apple. Your job is to assure that the silicon is designed to meet Apple's ESD specifications and manufacturing requirements. The role involves working closely with different cross functional teams within Apple as well as external vendors. Occasional travel might be required.

Key Qualifications

  • The ideal candidate will have the following qualifications:
  • Minimum 7 years of experience
  • Solid understanding of transistor device characteristics
  • Solid understanding of models used for testing ESD, including HBM, CDM, MM and IEC-61000-4-2
  • Knowledge of state-of-the-art ESD circuit design techniques and topologies
  • Hands-on experience with design/layout EDA tools, including Virtuoso, Calibre, Allegro, etc.
  • Knowledge of ESD checking tools like PERC and Pathfinder
  • Experience with Si processes used for high voltage, RF, and advanced ASICs
  • Experience with ESD/LUP test and characterization equipment
  • Strong initiative and ownership of responsibilities, productive, able to meet aggressive deadlines
  • Excellent written and verbal communication skills 


It is your responsibility to: Define the ESD methodology for all ICs developed by Apple and to specify the chip and IP level ESD requirements. Design ESD protection devices and circuits to meet design requirements. Develop test structures to characterize Si for ESD/LUP properties. Develop design rules based on Si characterization data. Interface with foundry on ESD library and ESD/LUP rule development activities. Maintain an ESD device library to support internal and external design teams. Generate or review ESD/LUP testing plans for Apple and vendor ICs. Manage the sign-off reviews with internal design teams, external vendors and foundries. Drive ESD/LUP related debug activities.


BSEE / MSEE is required