DV Engineers

Confidential Company  •  Austin, TX and 3 other locations

5 - 7 years experience  •  Engineering Services

Salary depends on experience
Posted on 11/08/17 by Bajrang Yadav
Confidential Company
Austin, TX
5 - 7 years experience
Engineering Services
Salary depends on experience
Posted on 11/08/17 Bajrang Yadav

5-7 years of IP, SoC Validation with System Verilog, UVM methodology

• AXI-4 expertise, experience in integration and validation with Cadence VIP's strongly desired.

• Experience in writing Systerm Verilog assertions and functional coverage cover-points/groups and analysis

• Proficient in C++

• Debug experience using waveforms, timing diagrams and register dumps

• Excellent communication skills (both verbal and written). Need to work with remote teams and articulate complex fail scenarios•

• Module level verification

• • Test environment and regression flow setup using standard Verilog/VHDL/System Verilog/Specman/System Verilog-OVM

• Test Cases development using standard Verilog/C-code/e-Specman/System Verilog-OVM/UVM and documentation

• Power aware test cases and simulations

• Regression test tracking and report

• Work with designer and Support design fix

• Support routine model-build, code turn-ins etc.

• Test generation in OVM/UVM and perl based flows for DFT and DFD features e.g. MBIST/ SCAN/ TAP

• ATPG, *BIST, TAP based test pattern conversion for post silicon usage (Use of Industry + Client based flows)

• Work with Client Verification and Design leads to signoff feature through Log file and waveform reviews

• Netlist based OVM/UVM verification Test bench development (future ask)

• Functional Coverage and RTL Code Coverage coding, enabling and analysis

• Automation using scriptinglanguages like PERL, TCL, Cshell, Awk, SED

• Documentation of Test Plans, Verification Strategies, Integration guides, Release notes

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