Technical expert driving novel DSP architectures for next generation data center interconnect. You will join a team of highly skilled DSP systems engineers involved in design, simulation, and implementation of advanced signal processing algorithms for the physical layer of high speed copper and optical data communication system at speeds of 28G/56G/112G. The types of algorithms that will be implemented include: adaptive equalizers for advanced modulation schemes, clock and data recovery, error correcting codes, and calibration algorithms. Requires ability to work in a cross functional team environment to develop unique optical and SerDes platform solutions, as well as interactions with customers.
- Design and simulate DSP system architectures, define key capabilities and performance requirements.
- Interact closely with optics and analog teams to develop optimum system solutions.
- Create DSP and FEC hardware block specifications appropriate for RTL implementation.
- Perform research activities in digital signal processing for SerDes and optical channels.
- Work with designers to ensure circuit architecture can be efficiently implemented.
- Provide guidance on test plans for lab characterization once design comes back from fab.
- Develop/perform behavioral modeling of mixed-signal circuit designs for transceivers.
- M.S.E.E./Ph.D. with 5-10 years of experience with ADC-based PAM4 and/or coherent DSP architectures & algorithm development.
- Very knowledgeable about the common high-speed serial data protocols NRZ/PAM4 and system standards.
- Strong experience in communication system modeling in Matlab and/or Python.
- Experience in high-speed DSP, especially FFE/DFE/MLSE, Clock and Data Recovery (CDR) or FEC (algebraic codes, iteratively-decoded codes, high-speed decoder architecture) is a plus.
- Experience with high-speed/time interleaved ADC and the associated calibration algorithms is a plus.
- Team player, willing to take on a variety of projects, good listening skills, self-motivated.