DRAM Design / Verification Engineer

Micron Technology   •  

Boise, ID

Not Specified years

Posted 211 days ago

This job is no longer available.

Req. ID: 116844 

This is a scalable position as a Verification Engineer at Micron Technology, you will work in a highly innovative and motivated verification team using state of the art memory technologies to develop and verify the most advanced DRAM products.


  • You will be challenged by the complexity and difficulty of designing/verifying the high density memory chip with complicated functionality, ultra-high speed, advanced low power and power management technology.
  • You will on verification responsibilities with deep understanding the design to fully evaluate the design at chip or block level on functionality, then provide solution.
  • You will work closely with Micron's global design teams to contribute to the success of the design team by applying verification tools and techniques, providing verification status and summaries to specific designs as needed.
  • You will participate in developing digital/analog mix-signal verification methodology for advanced DRAM products, as well as design and implementation of mix-signal design verification environment.




  • Fully understand the design datasheet.
  • Study and learn the circuit design in detail. Understand the functionality and timing requirements of the circuitry.
  • Develop patterns and regressions to increase the function coverage for all DRAM architectures and features.
  • Provide support to design engineers, debug failures, manage bug tracking, and close coverage.
  • Co-work with international colleagues on developing new verification tools and flows to solve the verification difficulties.
  • Develop and maintain test benches and test vectors using digital and analog simulation tools.
  • Create new methods and flows to guide DRAM chip design from verification view.
  • Create verification plan from functionality specification and in coordination with architects.
  • Work with cross-functional group to define and develop DFT patterns.



  • Fluency in verification languages (System Verilog or equivalent) and methodologies (UVM or equivalent) is preferred.
  • Good debugging and problem-solving skills
  • Strong communication skills with the ability to convey complex technical concepts to other verification peers.
  • Experience defining coverage strategy and writing coverage model is a plus.
  • Basic understanding of CMOS circuit design is preferred
  • Familiar with analog/digital simulation tools, ie. HSPICE, VerilogHDL, FINESIM
  • Experience in SV, VPI coding preferred
  • Experience in UVM Test Bench preferred
  • Must possess good communication skills and ability to work well in a team
  • Previous work experience in DRAM memory related fields is a plus
  • Experience with SystemVerilog Assertion (SVA) is a plus.




BS or MS in Electrical Engineering, or equivalent, is required.

We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law.  This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.

Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.