You will help us on most advanced optical Ethernet transceiver design, including digital RTL design, verification and chip integration. Specifically, you'll help the team on developing verification test plans and test cases that cover all system features of complex chip, writing/debugging test code/ testbenches, and working closely with the design team to ensure timely delivery and quality designs.
The optical Ethernet transceiver is based on the latest CMOS IC manufacture technology with advanced PHY transceiver architecture to provide high performance and low cost solutions for hyperscale data center, enterprise and mobile infrastructure applications.
Our team is responsible for the most advanced optical Ethernet transceiver design including PHY system DSP algorithms, high speed analog, high speed DSP, digital design and verification. You have a rare opportunity to join this disruptive, and fast-paced IC design engineer team to explore ultra-high speed PHY transceiver design
You have experience in the latest design verification methodology such as UVM, assertion based coverage driven verification, and Objected Oriented Programming. You are proficient in modern design verification tools and languages (e.g. SystemVerilog, SVA, C++/SystemC, Perl, Unix Shell script). You have thorough knowledge verifying complex designs at SOC/chip and block levels. You have experience in the chip level verification environments setup, code/function coverage collection, and gate-level verification setup. You are proficient in SV/UVM based verification, and you have in-depth knowledge of digital logic design and ASIC COT design flow. You have strong scripting, debugging and problem solving skills.
Valid Through: 2019-11-12