Digital DFT Senior Staff Engineer

Overview

Do you enjoy working in a creative fast-growing entrepreneurial environment? With indie you´ll never walk alone! We place high value on our teams and pursue excellence for our employees and customers!

indie is empowering the Autotech revolution with next generation automotive semiconductors and software platforms. We focus on edge sensors spanning multiple modalities including LiDAR, radar, ultrasound and vision for Advanced Driver Assistance Systems (ADAS), autonomous vehicles, connected car, user experience and electrification applications. This position will report to our Symeo team. Symeo, an indie Semiconductor company, is a developer and manufacturer of innovative radar devices combining, high-frequency radar technology and communication to improve existing technology and enable new and emerging applications.

The design team at indie Semiconductor develops custom automotive centric ICs and System-on-Chips (SoCs) using Arm® based microcontrollers and integrating analog and mixed signal, RF and Power Management IPs. The engineer in this position will join a team of highly competent engineers that are creating brand new designs in the field of ADAS and sensing systems, power management, high speed converters, wireless and USB power delivery and connectivity (LIN, CAN, Ethernet). The digital design team at Indie semiconductor seeks a DFT engineer who will execute all aspects of pre-silicon DFT insertion and verification and interface with test engineering team for ATE test program development and silicon bring up. This position will report to the Digital Physical Design and DFT Director.

Responsibilities

• Definition of DFT requirements and architecture based on project specification and IP’s content.
• Implement and verify standard DFT techniques such as Scan, LBIST, MBIST and Boundary Scan.
• Work with Analog and Mixed signal designers to define and implement custom test logic for time effective IP testing.
• Analyze chip and block test coverage and generate test patterns for ATE.
• Generate test patterns for ATE including custom patterns for IP’s and functional test to improve test coverage or screen test escapes.
• Support post-silicon ATE test program bring up and test time reduction.

Requirements

With us, you must love being part of an organization where everyone makes a difference and contributes to the company’s success. Creativity, Ownership and Excellence are what we value.

These are the skills and know how an ideal candidate would bring. We understand that nobody is perfect! After all, your new job should challenge you and you should have the possibilities to grow.

• 8+ years industry experience in the implementation and verification of DFT/DFD techniques for digital and mixed signal designs. A strong fundamental knowledge of DFT is required.
• Understanding of core-based test methodology and scan isolation.
• Understanding of various fault models such as Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware.
• Knowledge in JTAG, Scan Compression, ATPG, Fault Simulation, at-speed testing and MBIST.
• Knowledge in test methodologies for mixed signal IP’s like ADC, DAC, Serdes.
• Experience in self-testing technique (LBIST and MBIST) to achieve functional safety requirements for Automotive products.
• Familiarity with System Verilog, UVM, and use of assertions during verification, is preferred.
• MS degree in Electrical and/or Computer Engineering
• Great communication skills

indie Semiconductor and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.