IDT is looking for a talented individual for their memory interface products. We are looking for a candidate with a strong background in several areas of IC development. These areas are architecture, RTL digitaldesign, and design back-end. Candidate will work with device specifications and develop digital sections of the device. This candidate needs strong debugging skills to design and create solutions to challenging memory interface issues. Candidate will work closely with applications and test engineering.
Expertise in Verilog RTL digitaldesign in high speed, mixed signal chip in deep submicron technology is required. Good understanding of high speed design, synchronization and timing is needed.
Good experience in using static timing tools, design for test tools, and interfacing with place and route team is essential.
Experience in successful tape-out of deep submicron chips is required. Experience in DDR DRAM interface chip design is a plus.
Great attitude, self-motivation, communication skills and excellent team work is a must.
Preferred Skills & Knowledge:
Expertise in custom schematic digitaldesign that optimizes for very high speed, high performance is a strong plus.
Education and/or Experience:
BSEE or MSEE in Electrical Engineering with a minimum of 10+ years of industrialexperience in CMOS RTL digitaldesign. Position level will be commensurate to experience.
Ideal candidate has 5+ years of relevant industry manager level experience in DDR DigitalDesign.