Digital Design Engineer Lead - CSM

8 - 10 years experience  •  Business Services

Salary depends on experience
Posted on 09/22/17
Santa Clara, CA
8 - 10 years experience
Business Services
Salary depends on experience
Posted on 09/22/17

Digital Design Engineer Lead - CSM

  • Job Number: 45565867
  • Santa Clara Valley, California, United States
  • Posted: 13-Sep-2017
  • Weekly Hours: 40.00

Job Summary

Imagine what you could do here. At Apple, great designs are needed to enable great products and customer experiences. Bring passion and dedication to your job and there's no telling what you could accomplish. In this role, you will play an important role of assisting the system team in silicon architecture, taking that definition to drive implementation and methodology for custom silicon. The success of these silicons have significant impact on all our products.

Key Qualifications

  • 7+ years of digital design experience.
  • 3+ years of management experience in managing a digital design team.
  • Drive and improve digital design methodology to meet high quality first silicon (Expertise in digital design methodology is necessary).
  • Hands on experience with silicon bringup, characterization and debug necessary.
  • Knowledgeable enough in all aspects of different types of silicon, including mixed-signal silicon.
  • Must also have knowledge of the general industry trends and technical challenges.
  • Experience in specific domain (MCU, SoC, FPGA) is a plus.
  • Must be able to appreciate the challenge as the point person to hold high standards in engineering as well as helping to clarify requirements to enable high quality silicon.

Description

Assist in architecture, implementation, verification and emulation of custom silicon. Trade off specific issues against system limitations. Help improve engineering requirements specification documents for custom silicon. Work with internal teams to assure that documents meet needs. Work with external vendors in developing micro-architecture, verification and emulation of custom silicon. Drive vendor’s methodology to meet Apple standard. Target to achieve bug free silicon to meet product schedule.

Education

BS required / MS or PhD preferred

Additional Requirements

Some travel may be necessary.

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