DFT Engineer


Fort Collins, CO

Industry: Consulting


Not Specified years

Posted 389 days ago

  by    Bala Krishna

·        SCAN stuck-at and at-speed techniques. Fundamentals of SCAN stuck-at and at-speed techniques. 

·        Expertise in handling Mentor Graphics EDT logic. 

·        Knowledge on On chip clock controller (OCC).

·        Pattern generation with Mentor Graphics TestKompress Tool.

·        Good knowledge in BSCAN operations. Knowleedge in MBIST Operations.

·        Expertise in handling Synopsys SMS tool sets (Integrator, Builder, Yield Accelerator).

·        Excellent track of pattern simulation and coverage analysis

·        Experience in ATPG, Scan, BIST and Mentor TestKompress. 

·        Expert in writing test benches (Verilog, system Verilog) and tests for different components like PLL, ADC etc for generating ATE vectors.

·        Experienced engineers with DFT flow, ATPG, Scan, BIST and Mentor TestKompress. 

·        Experience with the mentor tool sets. 

·        Familiarity with scan, membist, jtag concepts and 3rd party tools. 

·        Tester program creation, debug, and validation of DFT features on ATE.

·        Chip-level DFT insertion with sound knowledge of scan compression, MBIST& JTAG techniques

·        Should have good post silicon DFT bringup and debug experience

·        Hands on in multi-vendor DFT tools

Desired Candidate Profile

Candidate should possess a Bachelors or Masters degree in Computer / Electrical / Electronic Engineering with 4+ yr experience. Strong knowledge of DFT architecture , design , methodologies and tools - Scan , MBIST , Analog DFT , JTAG , etc. Hands on experience with minimum of 4years design / validation experience with strong / proven debug skills. 

$80K - $110K