- Job Number: 113009681
- Santa Clara Valley, California, United States
- Posted: 07-Sep-2017
- Weekly Hours: 40.00
In this highly visible role, you will be at the center of a System On Chip design effort interfacing with all disciplines, with a critical impact on getting functional products to millions of customers quickly.
- The ideal candidate will have 5+ years of DFT experience, leading DFT efforts for large processor and/or SOC designs:
- Knowledge of Verilog HDL and experience with simulators and waveform debugging tools
- Expertise in industrial standards and practices in DFT, including JTAG, ATPG, MBIST and trade-offs between test quality and test time
- Expertise in debugging ATPG patterns, MBIST setup/patterns, and JTAG/1500 related issues
- Experience on analog IP tests or test setup (PLL, high speed IO, ADC/DAC, and so on) will be a big plus
- Ability to conduct experiments during silicon debug, gathering and analyzing data; and utilize scripting to support efficient handling of ATE data
- Solid Understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon
- Experience with front-end design methodology including STA, Formal Verification, Synthesis, Linting, CDC, and so on.
As a DFT engineer, you will have responsibilities spanning various aspects: Implementing DFT infrastructure Developing and implementing DFT architecture Working with designers to integrate DFT implementations and run various checks Working with the DV team to verify DFT implementations and review verification coverage Managing schedules and supporting cross-functional engineering effort Working with test engineers to bring up test patterns on silicon Working with rest of the team to document DFT specifications Generating structural test patterns and analyzing and improving coverage
BSEE / MSEE is required