Master’s Degree in ElectricalEngineering with 10+ years of Industry experience
Ability to define DFT Architectures for Complex SoCs and Sub-systems
Good knowledge of On-chip scans compression or BIST techniques and test time reduction.
Memory BIST integration in SoC and verification, selecting the optimal mem.
Good knowledge of Hierarchical scan synthesis with Scan segmentation, Test models
Handle module level scan insertion.
Handle device scan insertion with multiple clock domains.
Able to do Block/ Device level pattern generation and simulations.
Scan interleaved with memory bist patterns gen and validation.
Device level transition delay testing with multiple clocks and handling exceptions.
Path Delay tests, delay coverage analysis.
Able to do Silicon debug and diagnostics
Delay tests using PLL, silicon debug and diagnostics