Design Verification Engineers

5 - 7 years experience  • 

Salary depends on experience
Posted on 03/21/18
Austin, TX
5 - 7 years experience
Salary depends on experience
Posted on 03/21/18

Semiconductordesign verification engineers needed in Austin, TX
Estimated Contract Duration: 1 year
Open Positions: 3

• GPU experience would be great; CPU experience would be fine as well; system level experience.
• Knowledge of UVM, SV, some SW skills like C++ or object oriented knowledge would be good.
• Write tests at top level; some test bench components.
• Debug skills.
• Improving debug efficiency; coordinating with emulation team members.
• code coverage; functional coverage; debug; nightly regression triage; system Verilog; UVM; cache and memory system experience is a plus; minimum experience is 5 years.
• 5+ year experience with UVM and SV knowledge.
• Graphics background is a plus but not a necessity.
• Knowledge of functional coverage; write cover groups.

Id : 3507

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