We are looking for a Staff Design Verification Engineer. The candidate must have proven record of verifying complex designs leading to successful field proven products. The candidate is also expected to contribute to verification methodology / flow in an IC design environment. Non-technical responsibilities will include schedule & deliverable management from team members. The candidate will work closely with the team of system architects and design engineers.
- Technical leadership, own chip and block level verification.
- Define chip level verification and lead / technically manage all verification activities for specific product, including schedule and deliverables.
- Work with digital design engineering to debug test cases in RTL and Gate Level simulation environment.
- Post-silicon debug and correlation.
- BSEE/MSEE/PHD with minimum 8/4/2 years of experience in verification of multi-million gate IC designs.
- Experience in entire verification flow including planning, testbench creation, RTL/gate level simulations to coverage and signoffs.
- SystemVerilog (VMM, OVM or UVM). UVM preferred.
- Scripting perl/python for flow support.
- Experience in uController based designs.
- Quick Learner.
- Team player.
- Good Communication skills.
Highly Desired Experience / Skills
- 2-3 years verification lead for multiple chips.
- Verification experience in some of following areas:
- High speed DSP, network, or switching controllers.
- High speed ADC/DAC/SERDES.
- Knowledge/Prior experience in IEEE 802.3 related 100G PHYs