Design Verification Engineer – Design Engineer2 (E.4) Memory Controller & PHY-IO IP Verification Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team! Xilinx’s SAV Verification group is looking for a Design Verification Engineer to contribute on high speed Memory Controller and PHY/IO IP Verification. The individual will help design, develop and use digital simulation and/or formal based verification environments, at block and full chip FPGA level, to prove the functional correctness of DDR, LPDDR, RLDRAM, QDR, HBM Memory Controllers, PHY/IO, and Network On-Chip (NOC) IPs, Subsystem, and SOC designs. Responsibilities:
Candidate is expected to be a strong team player with good communication skills and one who is capable to work independently with an eye towards improving overall product quality.