Req. ID: 115443
As a Design Verification Engineer within the 3DXP Media System Engineering at Micron, you will be responsible for defining efficient and coverage-driven testbench for high-quality design delivery.
- DV environment development in SV/UVM and SV/C.
- Design verification at RTL/Gate level, DV Coverage analysis, Coverage improvement at block and Chip level.
- Support of assertion and coverage-driven methodology
- Develop test cases in C/C++ to verify functional operation of that the system level.
- Power and Performance analysis
- Solid knowledge and experience in SystemVerilog object-oriented language
- Solid knowledge and experience of TestBench development in SystemVerilog
- Experience in verification methodologies such as UVM
- Experience in behavioral model development
- Experience in scripting language such as TCL and PERL
- Nice to have experience in non-volatile memory designs such as NAND flash
- Good communication skills and cross-functional teamwork
- MS degree in Electrical Engineering (or related fields) or B.S. degree in Electrical Engineering (or related fields) with 3+ years of industry experience.
We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law. This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.
Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.
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