Design Verification Engineer

Facebook   •  

Menlo Park, CA

Industry: Technology

  •  

Less than 5 years

Posted 121 days ago

As a Design Verification Engineer at Oculus, you willwork with a world-class group of researchers and engineers, and use yourdigital design and verifications skills to implement the testinginfrastructure to validate new core IP implementations and contribute to development and optimization of state of the art vision and sensing algorithms. You willwork closelywith researchers, architects and designers in creating test bench requirements and test cases for multiple state of the art IPs.

Responsibilities

  • Work with researchers and architects defining verification methodologies for each of the different core IP
  • Define and track detailed test plans for the different modules and top levels
  • Implement scalable test benches including checkers, reference models, coverage groups in System Verilog
  • Keep track of coverage metrics and bugs encountered and fixed
  • Implement self-testing directed and random tests
  • Support post silicon bringup and debug activities
  • Ability to communicate clearly

Minimum Qualifications

  • 3+ years of System Verilog OVM/UVM DV experience
  • Knowledge of Python, Perl, shell scripting
  • Knowledge with assertions (SVA) or others
  • Understanding of digital ASICs design flows
  • BS in Electrical Engineering or Computer Science or equivalent experience

Preferred Qualifications

  • C, C++ coding, debugging experience
  • Experience as a digital design engineer
  • Experience with low power design
  • FPGA implementation and debug experience
  • Self-motivated and team player
  • MS EE