Casa Systems, Inc., is a leading provider of next-generation ultra-broadband distributed and virtualized architectures in mobile, fixed telecom and cable networks. As the original supplier of commercially deployed CCAP systems that delivers voice, video, and data over a single port, Casa continues a tradition that brings leading edge solutions to hundreds of service providers around the world. At Casa Systems, our mission is to deliver ultra-broadband solutions that keep families, communities and the world connected. We harness our passion for innovation to drive technological solutions that allow service providers to do amazing things that improve the way we live.
We are seeking to hire a Design Verification Engineer to join our Hardware Engineering team based in Andover, MA, USA which is located about 30 minutes north of Boston.
The Design Verification Engineer will impact the organization by participating in the verification effort. This individual will be a member of the FPGA system, full chip, and block level verification team and will be responsible for developing the verification environment; developing test plans and verifying the function of the FPGA.
ESSENTIAL DUTIES & RESPONSIBILITIES:
- Work closely with FPGA and design verification engineers to advance and improve the verification environment.
- Create and/or enhance test benches by developing an understanding of the design under test.
- Define and build test benches for module/block level verification.
- Contribute to test plans for module/block level (IP) and system level verification.
- Identify and write coverage measures for stimulus and corner-cases.
- Define, implement, automate, and execute regression tests.
- Undergraduate degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experiencerequired. Graduate degreepreferred.
- 5+ to 7 years of design verification experience with a proven track record of successfully verifying and delivering complex ASICs, FPGAs or SoC.
- Working knowledge of functional verification including: test plan development, stimulus generation, functional coverage, monitors, checkers, scoreboards, and sequencers.
- Experience in one of the following: UVM/OVM/VMM, and constrained-random simulation.
- Conversant in Verilog/System Verilog.
- Some experience with one or more scriptinglanguages such as Perl, Python, or TCL a plus.
- Some experience with industry standard protocols such as DDR, I2C, SPI, and/or Packet Flow experience.
- Familiar with simulation environment using Xilinx and/or Altera FPGAs, a plus.
- A passion learning new technology, solving complex problems, and delivering on quality.
- Creative problem solving skills, attention to detail, and good coding skills are required.
- Capable of driving tasks to completion with some direction.
- Must have good teamwork and interpersonal skills.
Tracking Code 772