Design Verification Engineer

5 - 7 years experience  •  Business Services

Salary depends on experience
Posted on 09/21/17
Santa Clara, CA
5 - 7 years experience
Business Services
Salary depends on experience
Posted on 09/21/17

Design Verification Engineer

  • Job Number: 113056408
  • Santa Clara Valley, California, United States
  • Posted: Sep. 20, 2017
  • Weekly Hours: 40.00

Job Summary

Do your life’s best work here at Apple! This role is for a DV engineer who will enable bug-free first silicon for the mixed-signal designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Key Qualifications

  • Required: Advanced knowledge of systemverilog test-bench language and UVM
  • Required: Experience developing scalable and portable test-benches
  • Required: Experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations
  • Strongly Preferred: Experience with mixed signal verification methodology
  • Strongly Preferred: In lieu of UVM knowledge, C/C++ expert level knowledge
  • Strongly Preferred: Experience with DDR PHY or Controller
  • Preferred: Excellent knowledge of one of the scripting languages: Python, Perl, TCL
  • Preferred: Knowledge of formal verification methodology


In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture Develop verification methodology suitable for the IP, ensuring scalable and portable environment Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage Develop verification plans for all features under your care Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures Develop block, IP and SoC level test-benches Track and report DV progress using a variety of metrics, including bugs and coverage Develop mixed-signal simulation environment, and work closely with analog team to ensure overall bug-free mixed-signal design


MS + 3 years industrial experience BS + 5 years industrial experience

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