Design Engineer - Verification in San Jose, CA

$80K - $100K(Ladders Estimates)

Cray   •  

San Jose, CA 95101

Industry: Information Technology

  •  

Not Specified years

Posted 62 days ago

This job is no longer available.

At Cray we're always looking way down the road … years, even decades into the future. We're not developing products for next quarter. We're developing products for questions our customers might not even know they have yet. That's how high-performance computing works. So as you can imagine, we pay very close attention to what's coming … and that includes the next generation of computer scientists and engineers. These individuals are going to be the ones shouldering an awesome responsibility in the coming decades as big data gets bigger, artificial intelligence flexes its muscles more and more, and problems grow in complexity.

Required Responsibilities:


• Create testbench specifications and coverage plans

• Implement constrained-random sequences, agents, and environments using the UVM methodology

• Collaborate with designers to debug failures

• Interface with prototype lab and software teams after component integration



Required Skills and Background:


• BS degree or equivalent experience; MS preferred

• Experience architecting and creating test benches with standard verification languages

• Fluency with at least one programming language (Golang, Python/Perl, or similar)

• Excellent communication skills including the ability to clearly articulate concepts (in verbal and written form) to stakeholders inside Cray

• Ability to work well in a distributed team environment with lively debate

• Experience implementing automation infrastructure

• Experience integrating 3rd-party verification IP for industry-standard busses

Keywords:

ASIC verification, UVM, testbench, scripting, Python, assertions, coverage, stimulus, scoreboard, SoC, constrained-random, BFM, VIP

Valid Through: 2019-9-16