Data Flow Architect


Santa Clara, CA

Industry: Engineering Services


11 - 15 years

Posted 370 days ago

  by    Bajrang Yadav

Master’s Degree /Phd in Electrical Engineering with 10+ Years of Industry experience

Experience in Data Path functions, Packet processing, Memory Architectures including HBM

Protocol level experience with PCIE Gen 3/4

Develop micro-architecture including block diagrams, timing diagrams, pipeline diagrams.

Experience in HDL design with Verilog/System Verilog

Experience with ASIC and/or SoC design flows and methodology, including CPF/UPF flows

Ability to estimate power based on Preliminary RTL code.

Experience with industry standard RTL design, simulation, and formal verification tools

Experience in synthesis and development of timing constraints

RTL implementation experience based on High level Architecture Specifications

Experience working with DFx engineers to define and scope design requirements and develop specifications for testing a given IP on a test chip

Master’s Degree in Electrical Engineering with 10+ years of Industry Experience

Experience in creating IP and Full Chip level verification plan and test-benches from scratch using Verilog/SystemVerilog/OVM/UVM

Experience in architecture and validation of CPUs, SOCs and industry standard IPs

Experience with development and usage of BFMs, transactors and protocol checkers used in simulation and HW emulation

Experience with scripting in Perl/tcl/shell to automate flows

Knowledge in IP and SOC development flows and methodologies

Proficient in all aspects of pre-silicon validation (functional, DFT, power, coverage, gate level)

Experience developing models for hardware components in C/C++, SystemC or equivalent languages

Experience in delivering IPs or integrating IPs working with internal and external customers

Create validation plan using product/IP specifications/customer requirements and implementing the necessary verification environment

$80K - $160K