Master’s Degree /Phd in ElectricalEngineering with 15+ years of Industry experience
Experience in Architecting CPU functions such as ALU, Instruction Fetch and Decode units
Develop micro-architecture including block diagrams, timing diagrams, pipeline diagrams.
Experience in HDL design with Verilog/System Verilog
Experience with ASIC and/or SoC design flows and methodology, including CPF/UPF flows
Ability to estimate power based on Preliminary RTL code.
Experience with industry standard RTL design, simulation, and formal verification tools
Experience in synthesis and development of timing constraints
RTL implementation experience based on High level Architecture Specifications
Experienceworking with DFx engineers to define and scope design requirements and develop specifications for testing a given IP on a test chip