Chip Level PD CAD Flow and Methodology Engineer
- Job Number: 113032720
- Santa Clara Valley, California, United States
- Posted: 14-Sep-2017
- Weekly Hours: 40.00
You will develop and support the top-level place and route methodology and flow. This flow is used by multiple projects at multiple sites. Strong knowledge of top level place and route flow, UPF, algorithm, scripting (TCL/Perl) and Makefiles are a must. You will interface with physical design teams, CAD team, and EDA vendors. Good communication/interpersonal skills are important.
- Candidate typically will have 15 years experience in hierarchical ASIC P&R and flow development.
- Experience with all aspects of ASIC PD including floorplanning, power-distribution, multi-voltage design, pad ring construction, placement, CTS, and routing.
- Understand hierarchical P&R issues including top-level floorplanning, pin-assignment, clock-distribution, critical-signal handling, UPF, MVRC, hierarchical abstractions (black-box, ILM, etc.), and dealing with pad-ring logic/IP.
- Strong TCL/Perl/Makefile scripting knowledge. Candidate should have experience developing complex algorithms, managing, and regressing P&R flows.
- Candidate should be familiar with chip-finishing issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologies.
- We are looking for a self motivated, proactive problem solver. Strong interpersonal/communication skills are a must.
- ICC or Encounter knowledge is a plus.
- Technical leadership experience is a plus.
Provide innovative solutions to improve quality of physical design. Work with chip design teams to implement and customize design flows that are optimal for a given chip. Provide documentation, training and new-user-support. Responsible for diagnosis, resolution, regression of reported problems for multiple projects/sites. Work with CAD team to integrate the flow into the larger infrastructure.
BS/MS EE/CS or equivalent