CAD Engineer – Transistor level SigEM analysis flow
- Job Number: 113000896
- Santa Clara Valley, California, United States
- Posted: 07-Sep-2017
- Weekly Hours: 40.00
In this highly visible role as a core team member in our advanced CAD Group, you will enhance your career working on state of the art designs. You’ll utilize your hands on experience in signal electro migration (SigEM) analysis to develop/define & refine the methodologies and flows for transistor, as well as gate level designs. The areas will include but not limited static and dynamic SigEM, powerEM, IR analysis and simulations, design abstract and reuse for EM and IR purposes, IP/SOC level EM and IR sign-off etc.
- Typically requires 5-15years of experience in EM and IR field in the following areas:
- Methodology for transistor level static and dynamic SigEM analysis with spice/fastSpice simulators, model abstraction
- Model creation and reuse for transistor level designs
- In-depth knowledge in industry leading tools, like Totem/Voltus-Fi/Redhawk/Voltus/ICC-EM, etc
- PNR level EM and IR analysis on different modes
- Knowledge in Extraction and STA methodology and tools
- Proficient in programming using PERL/TCL/Shell/C/C++ etc.
- Experienced with version control system, ie. CVS, Peforce, etc.
- Experience in the following areas would be nice:
- Layout, extraction, and simulation
- Flow regressions
- Circuit and physical design knowledge
- Power analysis
- Library characterization for EM and IR
Primary responsibilities include development of custom SigEM solutions; revamping/rewriting and streamlining the EM (SigEM and powerEM) and IR flows as well as assume ownership of entire domain. You will work closely with various design groups (Custom Digital/Analog/mix-signal/Power/Technology) on their EM and IR requirements for various post layout flows. You will also work closely with vendors/foundries for tool and technologyqualification and debug.
MSEE or BSEE or equivalent.