As a VLSI CAD methodology and applications engineer in the IP QA group, you will define, implement and support the methodology to build and verify IP collateral releases. You will be tasked to improve the quality of the releases and overall productivity of the design teams.
As a member of the software development team, you will interact with teams to plan, analyze, implement and maintain scalable software solutions. Your systems will handle hard IP including standard cell and IO libraries, Memories, PDKs and design collateral from internal and external design teams and foundries.
You will gain exposure to many IP views from different EDA tools/vendors and numerous design flows. You will set up Quality Assurance (QA) tests against these views using standard EDA tools. Exposure to these tools and flows will expand your knowledge to support the design team's releases.
You will organize and use databases to track metrics. Web based interfaces may be designed to visualize the data.
You will be working with a small, focused, skilled and dedicated team to contribute to different CAD responsibilities as they emerge. Strong analytical skills and effective interpersonal communication are important to this position.
BS or MS (preferred) in CE/EE/CS