+ Create and maintain block and IP level regressions
+ Maintain Graphiccs IP source code by integrating code among multiple source code repository locations
+ Create directed and random block level verification tests
+ Review functional and code coverage metrics – modify or add tests to meet coverage requirements
+ Debug test failures to determine if it is a design or verification issue; work with the design team to correct defects and test issues
+ Debug verification test failures observed on HW emulation testing of the Graphics IP
+ Must have a BS degree in Electrical or Computer Engineering (MS degree preferred).
+ Must have 5 years of experienced in ASIC verification.
+ Must be proficient in Verilog, System Verilog, C and C++, UVM, Perl, Unix shell scripting, makefiles and the make utility, and working in Linux and Windows environments
+ Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation tools
+ Must have a good knowledge of Software Engineering and excellent programming skills
+ Must demonstrate strong analytical thinking and problem solving skills with an excellent attention to detail
+ Must have good English hearing, speaking, reading and writing capabilities
+ Must have good teamwork and interpersonal skills
+ Graphics pipeline experience is preferred
Requisition Number: 60024