ASIC RTL Engineer

Google   •  

Mountain View, CA

Industry: Information Services


Not Specified years

Posted 297 days ago

This job is no longer available.

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. Google engineers develop the next-generation technologies that change how users connect, explore and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. You will be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and aren't daunted by the challenge of building something from scratch, then our team might be your next career step.

In this role, you will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, verification, power, timing, synthesis and etc. to deliver high quality RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions. You will evaluate design options with complexity, performance, power and area in mind.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Hardware team researches, designs, and develops new technologies and hardware to make our user's interaction with computing faster, more powerful, and seamless. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, our Hardware team is making people's lives better through technology.


  • Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline and etc.
  • Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
  • Participate in synthesis, timing/power closure and FPGA/silicon bring-up.
  • Participate in test plan and coverage analysis of the block and SOC-level verification.
  • Communicate and work with multi-disciplined and multi-site teams.



  • BA/BS degree in Electrical Engineering or equivalent practical experience.
  • Experience in ASIC development with Verilog or VHDL.
  • Experience with ASIC design verification, synthesis, timing/power analysis and DFT.


  • MSdegree in Electrical Engineering.
  • Knowledge of high performance and low power design techniques.
  • Knowledge of FPGA and emulation platforms. Knowledge of SOC architecture.
  • Knowledge of assertion-based formal verification.
  • Proficient with a scriptinglanguage like Perl.
  • Domain knowledge in one of these areas: memory compression, fabric, coherence, cache, DRAM, PHY.