Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
As a Power Engineer on the chip team, you will be working to architect power solutions for SoCs in advanced technology nodes. You will define and drive the power management and optimization methodology from architecture to implementation and sign-off. You will define the requirements for power management IPs and be responsible for the design, integration and post-silicon validation of the IP. You will set power budgets for use cases and provide power estimation for blocks and full chip, and you will collaborate with cross-functional teams to drive power reduction across the platform.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We're always on call to keep our networks up and running, ensuring our users have the best and fastest experience possible.
- Define and drive power methodology for design, verification and implementation of deep submicron SoCs, define and develop generic power management IPs to drive clock, reset and power controls, and define and develop innovative schemes to achieve power reduction from circuit to system level.
- Develop methodology and tools for implementing power reduction. Work with tool vendors to address any power-related tool or flow issues.
- Work with architects and logic designers to understand the power requirements and define all power specs and budgets.
- Verify and sign-off block and full-chip power intent using EDA tools.
- Estimate power for blocks and top-level using EDA tools and roll-up full-chip power.
- BS degree in Electrical Engineering or equivalent practical experience.
- 7 years of ASIC design flow experience.
- Experience with ASIC power analysis methodology.
- MSdegree in Electrical Engineering.
- Experience in design and analysis of power management IPs with a solid understanding of clock, reset, and power sequencing interactions, experience in low power digital ASIC design including UPF/CPF, multi-voltage domains, power gating and on chip power management, and experience in post-silicon validation and debug.
- Experience in Verilog, SystemVerilog, and RTL simulation, proficiency in programming languages (C/C++) and proficiency in scriptinglanguages (Tcl, Python, or Perl).
- A solid understanding of ASIC design flows and methodology including RTL, verification, synthesis, STA, formal verification on 28nm and 16nm process nodes.
- Extensive knowledge and experience using EDA tools like Conformal LP, Power-Artist, DC/RC, PT/PTPX, Incisive/VCS.
- Proficiency in gate-level SPICE simulations, and statistical SPICE models. Excellent verbal and written communication skills and a self-starter, motivated and strong team player.