$150K - $200K(Ladders Estimates)
Job Description and Requirements
In this role, you will be part of the DDR & HBM PHY hardening team overseeing development and implementation of DDR and HBM technical solutions for customer ASICs and SOCs. This includes all aspects of physical design, from front-end implementation (synthesis), through place and route, verification, design for test and ATPG. The successful candidate will contribute as a leader of both internal and external design teams. An ideal background would include hands-on, expert level physical design or implementation of ASICs / SOCs experience using Synopsys EDA toolset, in semiconductor technologies below 28nm.
The ideal candidate will have a strong desire to learn and explore new technologies. Demonstrates good analysis and problem-solving skills. You will be dealing with cutting edge technology from tier one silicon foundries and semiconductor manufacturers, as well as with most of the top companies in the world working on SOCs and ASICs. Typical work assignments will include analyzing customer's requirements and proposing solutions in terms of floorplan, bump map, design for test features, packaging, and silicon technology. Upon finalizing a solution, Design Lead would discuss the design ideas with implementation teams, and oversee their execution through all the development stages until delivery and integration into customer's SOC or ASIC. Additionally, candidate will serve as a conduit into R&D with ideas for product improvement based on actual implementation experience.
Valid Through: 2019-10-18