$80K — $100K *
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
This position of “ASIC Physical Design Engineer” is for a Design Implementation Engineer who will primarily work on the design flows that will enable physical design activities and who will also work on the physical design aspects to implement the digital hard macros in Synopsys DDR PHYs at the cutting edge technology nodes.
Tasks will include but not be limited to, scripting, debugging, testing and maintaining of flows and methodologies, documentation, running synthesis and P&R flow using Synopsys tools, performing timing closure, constraints analysis, static and dynamic IR drop analysis, power estimation, electromigration checks and other physical verification tasks such as DRC/LVS/ERC.
Additional tasks will include creation of views necessary for SOC integration of the hard macros and running all required QA checks before release of these views. The candidate will be expected to work independently to find solutions to complex design implementation issues and to analyze and suggest improvements to the design methodology and design flow.
Valid through: 4/13/2021