ASIC Physical Design Engineer at Synopsys Inc in Nepean, ON

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

Job Description:

This position of “ASIC Physical Design Engineer” is for a Design Implementation Engineer who will primarily work on the design flows that will enable physical design activities and who will also work on the physical design aspects to implement the digital hard macros in Synopsys DDR PHYs at the cutting edge technology nodes.

Responsibilities:

Tasks will include but not be limited to, scripting, debugging, testing and maintaining of flows and methodologies, documentation, running synthesis and P&R flow using Synopsys tools, performing timing closure, constraints analysis, static and dynamic IR drop analysis, power estimation, electromigration checks and other physical verification tasks such as DRC/LVS/ERC.

Additional tasks will include creation of views necessary for SOC integration of the hard macros and running all required QA checks before release of these views. The candidate will be expected to work independently to find solutions to complex design implementation issues and to analyze and suggest improvements to the design methodology and design flow.

Requirements:

• Requires a Bachelor’s degree in Electrical/Electronic Engineering (or equivalent) with 2+ years industry experience. Master’s degree is preferred
• Scripting skill and experience using languages such as Tcl, Python, and/or Perl.
• Proven ability to handle broad responsibility for block-level digital physical design from RTL to signoff.
• Successful experience completing physical design in an advanced wafer technology
• (ex: FinFET, 16nm, 14nm, 12nm, 7nm, 5nm).
• Understanding of digital logic and RTL circuit representation.
• Understanding of common design-for-test (DFT) implementation techniques.
• Understanding of signal integrity and power integrity.
• Strong understanding of timing constraints and static timing analysis.
• Strong engineering communication and collaboration skills.
• High motivation and determination to succeed.
• Previous experience with scripting-debugging flows & methodology, physical design of IPs or working with P&R tools is desirable