- Work in close collaboration with the front end designers and architects on the various SOC performace verification efforts.
- Interact with a wide variety of internal and external design verification development teams, DV methodology, and Silicon IP and tool vendors.
- Work with architects, and the design and DV team to develop functional and perfrormance Testplan.
- Focus on design and verification of deep sub-micron GPU chips including block/full chip level (full chip) design and verification.
- Responsible for multiple aspects in ASIC design flow and provide technically leadership to the engineering team.
- Accountable for project delivery.
- Familiar with Unix/Linux environment and good at scripts
- Good Understanding of dGPU SOC architecture.
- Proven debugging and problem analysis skills.
- Familiar with C/C++ modeling for simulation
- Experience with Building test bench and monitors for DUT
- Versatile in any one of the high level verification flow such as SV, UVM,VMM,VERA, etc as well as knowledge of industry standard tools for verification
- Excellent communication skills (both written and oral)
- Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experiences
Requisition Number: 63923