ASIC Design Verification Engineer, Consumer Hardware

Google   •  

Mountain View, CA

Industry: Information Services

  •  

Not Specified years

Posted 291 days ago

This job is no longer available.

Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

You will be part of a Research and Development team developing high performance and low power hardware and software to enable Google’s continuous innovations in mobile image, vision and AI processing. Your responsibilities include building verification components, constrained-random testing, end-to-end system testing, and verification closure.

Google's mission is to organize the world's information and make it universally accessible and useful. Only one thing consistently stands in the way between our users and the world's information - hardware. Our Hardware team researches, designs, and develops new technologies and hardware to make our user's interaction with computing faster, more powerful, and seamless. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, our Hardware team is making people's lives better through technology.

Responsibilities

  • Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
  • Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
  • Identify and write all types of coverage measures for stimulus and corner-cases.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Close coverage measures to identify verification holes and to show progress towards tape-out.

Qualifications

Minimumqualifications:

  • BS degree in Electrical Engineering or Computer Science or equivalent practical experience.
  • Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog for FPGAs, ASICs, and/or SoCs.
  • Experience verifying complex digital systems, such as ones that use standard IP components and interconnects, including microprocessor cores and hierarchical memory subsystems.
  • Experience with the creation of and usage of verification components and environments in a standard verification methodology such as VMM, OVM, or UVM.


Preferredqualifications:

  • Master's degree in Electrical Engineering or Computer Science with 3 years of relevant experience, or PhD in Electrical Engineering or Computer Science.
  • Experience with image processing, computer vision, and/or machine learning applications.
  • Experience with performance verification of SoCs and SoC components.
  • Experience prototyping and debugging systems on Field Programmable Gate Array (FPGA) platforms.
  • Experience with verification of low power techniques.
  • Familiarity with SoC standard interfaces and memory system architecture.