Job Description / Responsibilities:
Ostendo is seeking an experienced ASIC design manager to join the ASIC design team. She/he will develop and implement hardware designs from specifications into complex custom ASICs. The candidate will have technical management experience of leading ASIC engineers as well as hands-on experience designing ASICs. He/she will manage and do implementation of block level RTL, integration of blocks into full top-level (ASIC) RTL, logic synthesis, timing analysis (STA) and formal verification. She/he will also oversee and perform block level verification on test bench, build reference models, and perform test case development. He/she will also be involved in the floor planning, design budget partitioning, silicon validation, silicon bring-up, and characterization of the product. The candidate will participate in planning and execution of ASIC department designs and test activities with other ASIC managers, and report to the ASIC engineering director.
Skills / Experience:
- Proficiency in front end digital design tools and methodologies
- Good experience with processor design
- Experience in high level RTL VHDL coding / validation using simulators (e.g. Questa)
- Design knowledge of IO interfaces (e.g. I2C, SPI, USB, etc.)
- Interface design knowledge (i.e. MIPI, MHL, HDMI)
- Experience with embedded processors, DSP, graphics microprocessors
- Experience with IP selection and 3rd party IP vendors
- Ability to perform mixed language simulation (Verilog and VHDL)
- Experience in Verilog, System Verilog, VHDL, and scriptinglanguages (e.g. Perl)
- Experience with semiconductor foundries and EDA tools vendors is a plus.
M.S. degree in Electrical Engineering / Computer Science, or equivalent work experience
- A least 5 years managing a team of ASIC engineers
- A minimum of 10 years of ASIC and FPGAexperience with a track record from product conceptualization to characterization.