$100K - $150K(Ladders Estimates)
Job Description and Requirements
The Physical Design Specialist Application Engineer (PDS AE) will be an expert in Physical Design methodologies and flows to support the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.Understanding of Formal Verification, Synthesis (logical and physical) and Static Timing Analysis (STA) knowledge is desirable.
Experience with physical design implementation of blocks is required. Hands-on experience in all aspects of physical design implementation of blocks including placement, clock tree synthesis, routing and timing closure is required. Knowledge of floorplanning, multi voltage design, top level integration and DRC closure is preferred.
In addition, PDS AEs are expected to be able to articulate design methodologies involving Synopsys tools and be 'elevator-talk' proficient in the full Synopsys tool portfolio. Development time will be spent gaining expertise in additional, or specialization tools, broadening focus from product emphasis to methodology, sharpening Account Management skills, and learning to leverage success. PDS AEs support Account Managers to exceed quota; they also provide technical support to ensure customer success and satisfaction. PDS AEs are expected to manage multiple customer activities concurrently, and work with Account Managers and AE management to set their priorities. Sales support roles include product demonstrations, evaluations, and competitive benchmarking. Customer support roles include training, problem resolution, and technical account management. PDS AEs must be able to interact effectively with end-users at customer sites, as well as first level managers. PDS AEs also participate in account planning, where they work as part of the account team to develop the Synopsys solution to customer problems by bringing their understanding of customers' needs and issues. Some travel may be required.
Hands-on experience in all aspects of physical design including data preparation, placement, clock tree synthesis, routing, floorplanning, timing and DRC closure, and low power physical implementation. Experience with modern technology nodes (16nm and below) is required. Experience with library preparation and techfiles is desirable. Must possess at least five years of recent hands on experience in the place & route domain using Synopsys or competing Place&Route tools (direct IC Compiler 2 experience is preferred). Knowledge of areas ASIC implementation domains outside of place & route, including logic synthesis, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS and power analysis is a plus. Excellent verbal and written communication skills are required. Previous experience working with customers is a strong plus. Customer sensitivity, the ability to multiplex many issues & set priorities, and the desire to help customers exploit new technologies are essential for success in the position. BSEE or equivalent, required with 7 years of experience, or MSEE, or equivalent with 5 years of experience.
Valid Through: 2019-10-18