Applications Engineer - Formality in Sunnyvale, CA

$100K - $150K(Ladders Estimates)

Synopsys Inc   •  

Sunnyvale, CA 94086

Industry: Information Technology

  •  

8 - 10 years

Posted 53 days ago

Job Description and Requirements

Formality AE Job description:

The primary focus of the Formality Specialist Application Engineer (Formality AE) is to support the sale and adoption of Synopsys' Formality and Formality ECO products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects. Formality AEs are expected to possess Formal equivalence checking, Verilog and VHDL RTL coding, Synthesis and multi-voltage design experience and knowledge.

Experience with other aspects of the ASIC implementation flow including Design-for-Test (DfT), Physical Design, low power optimization/multi-voltage design implementation and verification using UPF is also desired. Development time will be spent gaining expertise in equivalence checking techniques and challenges, broadening focus from product emphasis to methodology, sharpening Account Management skills, and learning to leverage success.

Formality AEs support Account Managers to exceed quota; they also provide technical support to ensure customer success and satisfaction. Formality AEs are expected to manage multiple customer activities concurrently, and work with Account Managers and AE management to set their priorities. Sales support activities include product demonstrations, evaluations, and competitive benchmarking. Customer support activities include training, problem resolution, and technical account management. Formality AEs must be able to interact effectively with end-users at customer sites, as well as first level managers. Formality AEs will contribute to account planning activities where they will leverage their understanding of customers' needs and issues with the rest of the account team. Formality AEs also leverage their knowledge by writing Solv Net! Articles, and by assisting other AEs.

Requirements:

Design experience should include ASIC design using industry-standard hardware description languages (Verilog and VHDL). Excellent verbal and written presentation/communication skills are mandatory. Strong interest and understanding of design methodologies is required. Deep Synopsys front end tool (Logical and Physical Synthesis, Formal Verification, Verilog RTL coding, Low power/Multi-voltage flows) experience and knowledge are required. Physical Design and design-for-test experience is also highly desirable. Customer sensitivity, the ability to multiplex many issues & set priorities, and the desire to help customers exploit new technologies are essential for success in the position. BSEE or equivalent, required with 8 years of experience, or MSEE, or equivalent with 2 years of experience.

Valid Through: 2019-10-18