$80K — $100K *
1. Architecture study and evaluation of advanced SerDes topologies
2. SerDes design and verification of different high speed analog and mixed signal blocks including, but not limited to: drivers, front end circuits, samplers, comparators, ADCs, DACs, PLLs, clock distribution, etc.
3. Evaluate, measure, and debug silicon until it reaches high volume production.
4. Work with cross functional teams to optimize the designs
1. MS or above with a major in EE or Physics related field.
2. Solid background in high-speed analog CMOS circuit design
3. Familiar with serial links and wireline transceivers design and verification.
4. Proficient with Cadence design environment and mixed-signal simulation.
5. Familiar with RF system design and RFIC verification.
6. Familiar with ADS RF system simulation tool.
7. Familiar with ATE development related software
8. At least 2 years work experiment on cellular, BT or WiFi .
9. Excellent working attitude and good interpersonal and communication skills.
10. Able to assume responsibility for a variety of technical tasks and to work independently.
Valid through: 12/9/2021