Looking for an experienced analog designer to assist the Corporate R&D Analog Intellectual Property (AIP) organization. The candidate will primarily be designing analog IP with a focus on high speed I/O used in digital centric designs.
The designer should have experience working in a mixed signal environment that will focus on high speed I/O’s, PHY interfaces and be very familiar with industry standards. Typical analog development will include high speed I/O interfaces, PLL’s, A2D’s, D2A’s, and otheranalogcircuit designs used within system ASICs. Experience with system level modeling (System-Verilog), Analog modeling (Verilog-A), as well as standard digital modeling (Verilog) all required.
The candidate will take an active role in design definition, architecture evaluation and selection, circuit design and evaluation, as well as play an active role in reviews of analog/mixed signal IP and assist with documenting designs with full specifications.
The individual will also be a mentor to new and existing IC designers. The type of circuits the designer will be involved with varies but experience with a variety of different analog and high speed I/O interfaces is a plus. Processes can be both internal ON Semi processes as well as external foundry based designs.
The ideal candidate is a results-oriented self-starter able to develop architectures and designs which meet customer requirements. The person will take projects from concept to completion with limited supervision. Extensive product design experience a must and customer interface experience a plus. The designer should be familiar with the digital product integration flow with knowledge of the various views that will be required to support a digital integration (Encounter place and route) flow.
The designer should have experience designing full custom analog/digital mixed signal test chips using either an analog centric Cadence Virtuoso environment as well as be versed in the digital heavy Encounter place and route strategy.
Education and Experience requirements
- M.S.E.E. with 5+ years of experience or Ph.D. with 4+ years of experience in mixed signal design environments.
- Must have experience with analog design, high speed I/O and PHY design, layout, and circuit simulation techniques in sub-micron CMOS technologies.
- Experience with design of analog and mixed signal feedback control system in the context of high-speed transceivers, and data converters a plus
- Solid understanding of MOS device physics, analogcircuit design and layout techniques
-Good mathematical background and skill in using tools as MATLAB or others
- Experience with Cadence design environment including mixed signal and RF simulations. Experience and knowledge of SPECTRE RF is an advantage.
- Good understanding of high-speed layout considerations, such as parasitics, crosstalk, isolation, supply and bias distribution, etc.
- Hands-on lab verification experience a plus.
- Demonstrated ability to test, troubleshoot and characterize own designs
- Fundamentals of IC manufacturing, reliability, yield, DFM, DFT, etc.
- Demonstrated excellent problem solving skills
- Must be willing to assume responsibility for a wide variety of technical tasks
- Demonstrated mentoring capabilities to junior engineers
- Good communication and presentation skills
- US Citizen or permanent resident preferred