Analog Design Engineer, Senior II at Synopsys Inc in Markham, ON

As an analog design engineer in the PLL design team, the candidate would be responsible for system-level and circuit-level PLL design. PLL designs will support high-speed Serdes designs such as PCI-Express, Ethernet, JESD and CPRI, as well as other applications. The candidate will work with a team of designers based at Synopsys' sites in Markham, ON and Mississauga, ON.

Responsibilities and Duties

• Custom circuit design in deep-submicron and FINFET CMOS technologies
• Design of analog circuits such as VCOs, charge pumps and voltage regulators
• Design of high-speed digital circuits such as dividers and clock distribution paths
• Schematic entry and spice simulation of custom circuits
• PLL top-level modeling and simulation
• Provide mentoring and technical guidance to junior designers

Qualifications and Experience

• Post-graduate degree in analog CMOS circuit design, or equivalent experience
• 8+ years of experience in CMOS analog circuit design
• Strong organizational and time-management skills
• Detailed understanding of PLL loop operation and design
• Design of PLL circuit components such as VCO's, charge-pumps, regulators and high-speed dividers
• Design in deep-submicron and FINFET CMOS technologies
• Hspice, Finesim or similar spice-type simulators
• Schematic entry in Synopsys Custom Designer or similar tools
• Knowledge of digital timing in PrimeTime and/or Nanotime is an asset