Our team will welcome candidates with strong analytical and problem solving skills, good knowledge of ASIC hardware design and strong programing abilities and good communication skills. Prior knowledge of DFT is plus but not a must. We will help you gain the knowledge and skills necessary is DFT field as part of the on-the-job training.
Design-for-Test is a very unique cross functional field in ASIC design. Engineers working in this field in addition to learning DFT design specifics will also gain a lot of knowledge in ASIC clock and reset structures, low power design techniques such as power-gating voltage-domains, IOs, PHYs and PLL operations, etc…
The qualified candidate will work as part of Design-For-Test (DFT) team to perform some or all the below functions:
- Participate in SOC full Chip DFT feature and architecture definition
- Implement SOC DFT functions including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
- Perform verification on all DFT structures
- Generate and verify DFT structural patterns and functional patterns
- Participate in ATE bring-up and debug the DFT patterns on ATE
- Design and implement other DFX (debug, characterization, yield etc) logics
- BS in EE & CS, with 5+ years of industry experience.
- Hands on working experience on ASIC design and/or verification and/or testing/validation
- Should have strong problem solving skills
- Good English hearing, speaking, reading and writing capabilities and good communication skills.
- Experience with micro-processor design is a plus
- Strong knowledge of C++, System Verilog, UVM verification methodology is a plus.
- Experience in complex ASIC design in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip scan pattern compression and at-speed testing using PLL, memory BIST and repair, power-gating, on-chip debug logic – is a big plus but is not a must have requirement.
Requisition Number: 46361