As a Senior SystemVerilog/UVM Verification Engineer at BAE Systems, you will help develop a simulation test bench to simulate and verify complex VHDL FPGA designs that include ADC/DAC interfaces, DSP, and high speed SERDES. As a Senior Verification Engineer you will be expected to develop Universal Verification Components (UVCs) including agents, monitors, scoreboards, etc. You will develop test cases, collect coverage, run interactive and regression simulations. You will mentor junior engineers on the verification process. You are expected to understand the systems level design down to the individual FPGAs. You will be working with systems engineers, FPGA designers, and other verification engineers in a fast paced dynamic environment.
Minimum Education and Experience:
Bachelor's Degree and 5 years work experience or equivalent experience
Required Skills and Education:
Experience in SystemVerilog/UVM or OVMExperience in developing UVC's (Universal Verification Components-agents, monitors, scoreboards, etc) for test bench environments for unit and system level verification
Experience in verification using constrained random stimulus in a self-checking environment.
Experience with design and verification tools (Mentor Questa or Cadence).
Preferred Skills and Education:
Digital Signal Processing experience
VHDL Design experience