As an Emerging Memory (EM) Product Development Engineer at Micron Technology, Inc., you will be evaluating technologies that enable further memory scaling. A range of technologies will be targeted (PCM, RRAM, STTRAM, 3D, Crosspoint, FBC, etc.) for non-volatile, and volatile memories. You will be responsible for the development of memory-test patterns, analyzing electrical failures, improvement of yield as well as overall cell performance, debug, design, simulation and implementation of circuit and process changes on test chips. Additionally, you will work with Design, Process, and Manufacturing departments to enable learning on new cell technologies, ranging from single cell structures through test chip arrays.
Your responsibilities will include but are not limited to the following:
Support for Design:
- Determine design implications on manufacturability
- Determine how to test product features
- Determine limits for the outgoing defect specification
- Debug initial silicon and verify design features
Support characterization/design evaluation
- Determine root cause of problems (process related or design related)
- Develop characterization plan and feedback design margin to design
- Monitor and report on initial silicon progress
Support for Fab and Process Integration
- Support the Fab by updating the Fab engineers on customer issues and wafer probe test coverage
- Support root cause defect analysis
- Support unique fail mode analysis
- Conduct performance analysis for fab's Special Work Requests (SWRs)
Support for Array Reliability testing
- Develop electrical testing utilized by wafer Probe
- Support defect analysis with electrical characterization
- Support for Wafer Test
- Correlate test results generated in Probe
- Explain rational of tests in probe and help determine the most effective method to implement tests with coverage, potential overkill, and test time being the biggest factors
- Determine test algorithms to target specific fail mechanisms
- Verify that testing guarantees outgoing defect specifications
- Possess a thorough understanding of mainstream memory technologies such as DRAM, NAND, NOR, & SRAM.
- Possess familiarity with Circuit/Architecture issues facing Memory Cell performance.
- Be proficient with data analysis, DOE, and statistical techniques.
- Possess familiarity with programming languages such as Perl, Python, R, Matlab, or JSL.
- Possess prior industry experience in advanced semiconductor component memory array reliability testing.
- Willing and able to work weekends and / or evenings if necessary.
All job offers will be contingent upon a successful drug screening and background check.
Work Location: 8000 S. Federal Way, Boise, ID 83716
Hours of work: Usually 8 a.m. to 5 p.m., Monday through Friday- also must be willing to work nights and weekends when necessary.
Degree Required: BS or equivalent foreign education
Academic Discipline(s): Electrical or Electronic Engineering
Alternate Occupations Accepted: Electrical or Electronic Engineering
Experience Required: Two years of progressive post-graduate experience