Tasks/responsibilities include: analog transistor/gate level design and simulation; chip architecture, floorplanning, and simulation; behavioral modeling of IP; custom layout/place and route/verification; lab evaluation.
Contribute to overall product direction discussions. Applications support and classroom training for early adopters. Creation of test and training examples and documentation for all modules and ability to generate, automate and run QA test suites.
You can handle deadlines and pressure. Your projects will be one to four week efforts to analyze a customer's needs and provide a solution. Sometimes these answers are needed very quickly and you have to respond with quality answers just as quickly.