In this position, you will design engineering assignments including engineering and designing chip layout circuits, circuit checking, documenting specifications, modifying and evaluating semiconductor devices and components.
In this role, the selected candidate will be responsible for designing and developing signal processing/communication algorithms for wireless MIMO; conducting C/C++ and Matlab simulations to study end-to-end system performance under various impairment and channel propagation conditions.
In this role, you will perform detailed design work, assembly layout, systems engineering, configuration control, creating drawings and model based definition using CATIA V5 within Enovia, release engineering.
In this role, the selected candidate will be responsible for digital design and FPGA implementation of uC and USB subsystem Digital design aspects including ASIC RTL customization to port to FPGA, FPGA RTL verification and debugging, FPGA synthesis, and timing closure.
In this role, the selected candidate will participate on a project involved in the development of Asics, with emphasis in synthesis, timing closure, low power, place and route. Develop constraints, run synthesis placement, low Power checks, timing and power analysis.
The candidate will work hands on to develop new analysis and implementation methodologies and tools, and will work with the Qualcomm product testing, PD team, and synthesis teams to improve Qualcomms designs.
In this role, you will be responsible for developing design corresponding test plans, architecting and developing verification environments, verification of complex designs until coverage goals are achieved dynamically or statically, and completing all required verification activities at IP, sub - system, SoC, and system / architecture level to insure high quality commercial success of our products.