In this role, you will be responsible for
leading teams of engineers and technicians in performing site inspections, performing engineering analyses and designs, and preparing technical reports and/or construction documents (plans and specifications).
In this role, you will have the opportunity to utilize your hands on experience in parasitic extraction to develop/define&refine extraction and simulation methodologies for transistor as well as gate level designs.
In this role, the selected candidate will design custom CMOS circuits, translating logic description into circuit schematics by conducting feasibility studies to compare possible circuit level implementations of the logic description using the knowledge of various circuit topologies, circuit design styles and Register Transfer Level languages.
In this role, the selected candidate must have an experience working on RTL pre-silicon design (coding or debug) of DDR based memory subsystems; fluency in coding and debugging Verilog, System Verilog and scripting languages.
In this role, the successful candidate will convert subsystems into real-world final designs for integration into final product; work in a team environment to create and engineer digital design subsystems from concept through to tape-out.
In this job you will be responsible for designing and coding BIST structures, setting up synthesis and timing constraints, running synthesis, logic equivalence checkers, and other front end tools as required.