The role involves RTL performance analysis and microbenchmarking for the DRAM memory controller IP. The engineer will work closely with the architecture, design and modeling teams working on high-performance memory controller designs. He or she will drive microbenchmarking plans at the IP level, and support performance debug at the SOC level.
In this position, you will collaborate among various functional groups for DFT tree built ups, e.g. clocking and power, logic place and synthesis- Provide silicon bring-up support and debug- In-house toolset, flow and methodology development
In this role, you will lead projects that are geared toward preparing detailed scopes of work, improving control systems, instrumentation, and industrial processes to maintain efficiency and maximize profitability
In this role, you will responsible for developing technology frameworks and standard architectures that enable the design, implementation, operation and support of information technology systems and infrastructure, and that provide functional environments for technology prototyping, development, integrated testing, training, and production.
In this role, the successful candidate will convert subsystems into real-world final designs for integration into final product; work in a team environment to create and engineer digital design subsystems from concept through to tape-out.
In this role, you will be responsible for full electrical design ownership of systems and/or subsystems for future/next-gen network security platforms including, but no limited to, schematic capture, stackup design, layout guidance, layout simulations, bring-up, characterization, functional and stress testing, release to production.
In this role, the selected candidate will be developing Verification environments in SV/UVM with the goal to build an optimized environment to flush out bugs as quickly as possible to deliver a highly functional first silicon.
In this role, the selected candidate will drive physical synthesis, functional unit floor plan and placement improvements, timing/power improvements, and design closure on electrical analysis issues in a high frequency SAPR environment.
In this role, you will be responsible for
participate and lead in design of prototype and production intent engines for light duty, heavy duty and large engine clients; engine designs may be clean sheet or upgrades to meet new performance and emissions targets; develop standardized design and analytical processes.
The Senior Consultant Engineer / Architect responsible for driving and delivering on strategic planning, design, and support for a MPLS/IP backbone network infrastructure including routing, switching, capacity planning and monitoring.