In this role, the selected candidate will work on design and verification methodology for various ASIC designs using multiple techniques (simulation, model checking, assertion-based verification, equivalence checking, and theorem proving).
In this role, the selected candidate is responsible for the entire digital design flow from RTL to GDSII, including digital and mixed-signal circuits and systems that are integrated into integrated circuits (ICs), System-on-Chip (SoC) and complete chipsets that power Qualcomms wireless device portfolio.
The candidate will work hands on to develop new analysis and implementation methodologies and tools, and will work with the Qualcomm product testing, PD team, and synthesis teams to improve Qualcomms designs.
The RF SiP Design Engineer will deliver Front-End Module designs in a fast-paced team environment, and is required to work closely with RF IC design engineers to optimize a design by extensive co-simulation and co-design based on RF system knowledge.
The candidate will work with a group of 3 to 5 filter designers performing modeling, filter design, and device characterization. The candidate will present design reviews which are expected to demonstrate compliance to the specifications using simulation and measured results.
You will be responsible for design and development of IP and SOCs. This would include direct responsibility for digital SOC and IP development including architecture, microarchitecture, RTL, CDC, LINT, synthesis, STA, and LEC. - Technical oversight of deliverables to/from the verification, analog design, physical design, and DFT teams.
The Structural Engineer is a key part of the ViaSat team and will have a significant impact on the design, development and innovation of the structural integrity of avionics programs. You will utilize your engineering expertise and imagination to create the worlds next generation of mobile communications.
In this role, the selected candidate will work with the RTL design team on understanding design in context of physical design timing closure including development of timing constraints required for implementation.