In this role, the selected candidate will execute validation compliance test plans relating to Display and HDMI port on APU ASIC; collect, analyze compliance data and generate customer validation reports. Perform first level of debug for both silicon and setup issues.
In this role, you will be responsible for the development of methodologies, execution of validation plans, and debug of failures. Requires broad understanding of multiple system areas and requires interfaces with architecture.
In this role, the selected candidate will develop pre-silicon readiness and post-silicon plan to validate specific IPs/functional blocks within the SOC (covering both functional operation and electrical characteristics).
In this role, the successful candidate will develop and execute embedded tests on the lab bench environment during pre-silicon and post-silicon phases of the product development to ensure functionality and performance.