In this role, the selected candidate must have an experience working on RTL pre-silicon design (coding or debug) of DDR based memory subsystems; fluency in coding and debugging Verilog, System Verilog and scripting languages.
In this role, the selected candidate will design custom CMOS circuits, translating logic description into circuit schematics by conducting feasibility studies to compare possible circuit level implementations of the logic description using the knowledge of various circuit topologies, circuit design styles and Register Transfer Level languages.
In this job you will be responsible for designing and coding BIST structures, setting up synthesis and timing constraints, running synthesis, logic equivalence checkers, and other front end tools as required.
In this role, you will team up with some very smart peoplestrategists, designers, writers, engineers, and, most importantly, our clients, to solve their most complex business challenges whether its an experience, platform, product or utility.
In this role, you will be responsible for the architecture, maintenance, and enhancements of the InduSoft Driver technology, including Driver Standard, Driver Toolkit, and Communication APIs for creating drivers.
In this role, you will be responsible for the architecture, maintenance, and enhancements of the indusoft driver technology, including driver standard, driver toolkit, and communication apis for creating drivers.
In this role, you will develop high level and/or detailed storyboards, mock-ups, and prototypes to effectively communicate interaction and design ideas. The selected candidate will deliver work that's not only user-friendly, esthetically engaging, but which also produces results.
In this role, the successful candidate will convert subsystems into real-world final designs for integration into final product; work in a team environment to create and engineer digital design subsystems from concept through to tape-out.
In this role, you will have the opportunity to utilize your hands on experience in parasitic extraction to develop/define&refine extraction and simulation methodologies for transistor as well as gate level designs.
In this role, you will apply strategic thinking to deliver end-to-end user-centered experiences, with the creativity and judgment to translate vision into concepts and designs that illustrate simplicity despite underlying complexity or constraints.