In this role, the selected candidate will be responsible for the development of analog and mixed signal circuitry in high performance mixed signal audio processing IC's; will participate in all aspects of the design including specification, architectural development, transistor level design, layout supervision, chip level verification, and lab validation.
The successful candidate will work with a talented team that designs leading edge, high performance network security protection devices that reside in enterprise data centers and central offices to direct, inspect and filter malicious traffic.
In this role, the selected candidate will participate on a project involved in the development of Asics, with emphasis in synthesis, timing closure, low power, place and route. Develop constraints, run synthesis placement, low Power checks, timing and power analysis.
In this role, you will provide first line liaison support to Manufacturing for production problem resolution and assist and or coordinate any subsequent next level engagement required from Customers, Operations, Project Engineering, Stress, Certification, Materials, Manufacturing or other.
In this role, the selected candidate will
be responsible for the development services including template development, content development, Forms, surveys, RSS feeds, Search capabilities, web analytics, transaction-based services, CMS integration.
In this position, you will create bottoms up elements of chip design including but not limited to FET, cell, and block level custom layouts, FUB level floor plans, abstract view generation, RC extraction and schematictolayout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation.
In this role, you will provide test cell and project engineering support to advanced engine research team; establish and maintain working relationships with clients and department staff to accomplish project objectives.
In this role, the selected candidate will be responsible for verification planning, testbench development, failure analysis and resolution, coverage analysis and population, digital/mixed-signal modeling, directed/constraint-random test generation, and flow development.