In this role, the selected candidate will participate on a project involved in the development of Asics, with emphasis in synthesis, timing closure, low power, place and route. Develop constraints, run synthesis placement, low Power checks, timing and power analysis.
In this role, the selected candidate must have a proven developer of complex verification checkers and stimulus using OVM/UVM or equivalent; extensive experience in functional modeling of industry/internal interfaces with SystemVerilog/ C++.
In this role, the selected candidate must have the ability to structure and execute complex analysis, draw insights, and communicate summary findings/recommendations to senior management as well as the company customers.
In this role, the selected candidate will design custom CMOS circuits, translating logic description into circuit schematics by conducting feasibility studies to compare possible circuit level implementations of the logic description using the knowledge of various circuit topologies, circuit design styles and Register Transfer Level languages.
The successful candidate will work with a talented team that designs leading edge, high performance network security protection devices that reside in enterprise data centers and central offices to direct, inspect and filter malicious traffic.
In this role, the selected candidate will be responsible for verification planning, testbench development, failure analysis and resolution, coverage analysis and population, digital/mixed-signal modeling, directed/constraint-random test generation, and flow development.
In this role, the selected candidate will be responsible for the development of analog and mixed signal circuitry in high performance mixed signal audio processing IC's; will participate in all aspects of the design including specification, architectural development, transistor level design, layout supervision, chip level verification, and lab validation.
In this role, the selected candidate will
be responsible for the development services including template development, content development, Forms, surveys, RSS feeds, Search capabilities, web analytics, transaction-based services, CMS integration.
In this position, you will create bottoms up elements of chip design including but not limited to FET, cell, and block level custom layouts, FUB level floor plans, abstract view generation, RC extraction and schematictolayout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation.