In this role, the selected candidate will collaborate with architects to translate the block's functional requirements into the block micro architectural specification; responsible for implementing the block Register Transfer Level (RTL) in hardware description language.
In this role, you will solid understanding of concepts such as impedance matching, impedance transformation, distributed systems, passive RLC and resonant circuits, noise, linearity, bandwidth and stability.
This candidate is responsible for leading and performing the design of overhead transmission lines including structure spotting, structure configurations, foundations, insulation coordination and conductor sizing.
In this role, the selected candidate will participate in the performance modeling, analysis and microarchitecture of the company's future core designs. Responsibilities may include: cycle-accurate core computer microarchitecture performance simulator development, workload and trace analysis, microarchitecture development, RTL vs performance model correlation, post-silicon performance analysis.
In this role, the selected candidate will be responsible for synthesis, netlist generation, timing and logical equivalency checks, floor planning, budgeting, clock methodology and timing constraint management.
The candidate will be an entry level engineer working with a very experienced logic and circuit design team and responsible for driving the physical design sub blocks for the next generation microprocessors in a fast paced environment.
In this role, the selected candidate will design Improvements to Low Voltage Switchgear, Medium Voltage Switchgear, and other Power Distribution Products, use and/or develop tools necessary for engineering calculations using Mathcad, Pro/Mechanica, Excel spread sheet, ANSYS, and other simulation tools.
In this role, you will be responsible to
designs, defines and implements complex system requirements for customers and/or prepares studies and analyzes existing systems. Determines system specifications, input/output processes and working parameters for hardware/software compatibility.
In this role, the selected candidate will be responsible for substrate design & routing, SoC Floorplan/Pad-ring optimization, Design of RDL & AP layers, Ball Map generation/optimization, along with IP/IO cell optimization in collaboration with IP and Chip/System owners.
In this role, the selected candidate will perform pre-Silicon Functional Verification of next generation high performance Microprocessor designs - specifically Verification of custom DFT (Design For Test) features, logic and microarchitecture.
In this role, the selected candidate will drive debug and closure of regression signatures using waveform viewer and output files; and collaborate with the RTL designers and test bench owners to fix bugs.